JOP is the implementation of a small java processor with the JVM fitting in a FPGA.

Designs, builds: single board computers (SBC), peripherals, embedded systems, PCB design/layout, high level programming (industry leaders in Forth), custom design work; large line of stock products: f

Free on-line book by Philip J. Koopman, Jr. Read it on-line, or download it in several formats including 700k zip file. Published in 1989, the first book to explore a new breed of stack computers led

Stack-based processors, 5-bit words, 25 instructions, 7000 transistors, 80 MIPS, 50 milliwatts, low cost; designed by Chuck Moore, creator of Forth programming language.

Makes IGNITE I ROSC (Removed Operand Set Computer), PSC1000 32-bit embedded shBoom-based microprocessor line, many ISDN interface products, sophisticated antenna/radar technologies.

Embedded systems consultant for small (8/16-bit) and distributed microprocessor systems. Contract hardware and software development for most microcontrollers. Specialist: Forth, Assembly, C. By Bradfo

References, links to Forth and stack machines in various technologies.

Uses of Forth microprocessors and programming language: controllers for spacecraft flight systems, on-board payload experiments, ground support; hardware or software to build or test flight or ground

Philip J. Koopman, Jr., CMU page. Many reports, studies, links. Compares: CISC, RISC, Stack systems; 2 & 3 stack systems. Excellent resource.

1987 Rochester Forth Conference Proceedings. Four abstracts of Forth processor systems. This was the same conference at which the S.N. Baranoff papers were first publicized in the West.

Small, fast stack-based processor for FPGAs. CPU prototyped and debugged in ANS Forth. A simple RTL-specific language extension provides discrete event simulation for structural model of CPU and allow

Research project for high performance, low cost computing. Uses stack based instructions for a 4-way VLIW processor. Implemented in current technology, it would outrun high-end DSPs (TMS 320C6x, Tiger

Goal: dominate very low cost, low power, single core CPU market, and have the only ultra-high-end supercomputer on-a-chip system. Because the CPU core is so small, it is possible to put 1000s of cores

Minimal instruction set, small, low power 16-bit CPU optimized to run Forth on a Xilinx FPGA. When system is stable, VHDL source code for CPU and all other code will be released to make a full open so

Course on minimal processors: Guided Exploration of two FPGA-based CPU Designs, led by John Rible.